`include "../define.svh"
module Add_INT_top(
    input clk,
    input sys_rst_n,
    input [1:0]data_type,  //2'b00:INT4,2'b01:INT8,2'b10:FP16,2'b11:FP32
    input en,
    input signed [31:0] a_in,
    input signed [31:0] b_in,
    //output reg signed [31:0] c_out_reg,
    output signed [31:0] c_out,
    output reg c_valid
);
    //wire signed [31:0]c_out;

    wire signed [32:0] a_ext = {a_in[31], a_in};
    wire signed [32:0] b_ext = {b_in[31], b_in};
    wire signed [32:0] sum_ext = a_ext + b_ext;
    
    // 溢出检测：如果第33位与第32位不同，表示溢出
    wire overflow = (sum_ext[32] != sum_ext[31]);
    
    // 钳位处理
    wire signed [31:0] clamped_sum;
    assign clamped_sum = overflow ? 
                       (sum_ext[31] ? 32'h80000000 : 32'h7FFFFFFF) :  // 根据结果符号选择钳位值
                       sum_ext[31:0];                              // 正常结果
    
    // 输出结果
    assign c_out = clamped_sum;
    /* always @(posedge clk or negedge sys_rst_n) begin
        if (!sys_rst_n) begin
            c_out_reg <= 32'sd0;
        end 
        else if (en) begin
            c_out_reg <= c_out;
        end
    end  */

    always @(posedge clk) begin
            c_valid <= en;
    end

endmodule
